The present invention relates in general to interface circuits providing communication between computer systems and in particular to an interface circuit permitting a bus master connected to one computer bus to directly access data stored in a memory connected to another bus.
In some applications, several computer processors are interconnected so that they may communicate with each other as when one computer processor generates data for use by another. Some systems connect the computer processors to the same parallel computer bus and allow them to arbitrate for mastery of the bus, thereby to access the same main memory. In such systems, one processor may pass data to another by writing data to a main memory location read accessible to the other. To provide faster memory access, a computer processor on the bus may copy a block of data from an area of the low speed main memory into a higher speed cache memory and thereafter read and write access the data in the cache memory rather than in main memory. However, if another computer processor on the bus subsequently read accesses the same area of main memory, data read may be "obsolete" because it was not updated when corresponding data stored in cache memory was updated. Also, if another computer processor on the bus writes data to the area of main memory, corresponding data in cache memory becomes obsolete.
In the standard IEEE 896 bus (the "Futurebus"), to ensure coherency between corresponding data in the cache and main memory, when a first bus master seeks to read access a main memory address, it may assert a "SNOOP" signal on the Futurebus during the bus address cycle. If a second bus master on the Futurebus is using a cache memory for data stored at that memory address, the second bus master may assert a "retry" signal, causing the first bus master to relinquish control of Futurebus before completing the address cycle. At that point, the second bus master obtains control of the Futurebus and writes the appropriate data from cache memory back into main memory. Thereafter, when the first bus master again attempts to access the data in the main memory, the second bus master ignores the SNOOP signal and permits the first bus master to complete both address and data cycles.
When various computer processors employ differing parallel buses, it is not possible to directly connect the computer processors to the same bus. In such case, the processors must operate within separate computer systems utilizing separate buses and accessing separate local memories. Typically, each computer system includes one or more ports connected to its bus. The ports of the separate computers are interconnected so that when a first computer reads data out of its local memory and writes the data to its port, that port signals a port of a second computer that it has data to transfer. The port of the second computer then signals a computer processor within the second computer that incoming data is available. The second computer processor then obtains the data via the second computer port and stores the data in its local memory, the second computer exercising normal second bus protocol, if any, for maintaining cache consistency. However, the process of transferring data from a memory location on the first bus to a memory location on the second bus is slow because it requires several bus cycles and ties up processors in both systems.